The present invention relates to a semiconductor device and to a method of forming a semiconductor device.
The present invention is particularly concerned with high voltage/power semiconductor devices which can be used as discrete devices, in hybrid circuits and in power integrated circuits and is particularly concerned with field-effect transistors, such as power MOSFETs, insulated gate bipolar transistors (IGBTs) and other types of power devices such as diodes, transistors and thyristors.
For devices designed for use in integrated circuits, it is preferred that the main terminals (variously called the anode/cathode, drain/source and emitter/collector) and the control terminals (termed the gate or base) are placed at the surface of the device in order to be easily accessible. The main current flow is between the main terminals and is therefore principally lateral. Such devices are therefore typically referred to as lateral devices. Such devices are often integrated with low-voltage devices or circuits built in CMOS-type or other standard planar technologies to form power integrated circuits. Several high voltage/power devices may be integrated in the same chip. Isolation is provided between the high-power and the low-power devices as well as between adjacent power devices. Two principal isolation technologies have emerged, namely junction-isolation (JI) technology and silicon-on-insulator (SOI) technology.
In JI technology, a reverse-biased junction is used to isolate adjacent devices. However, this is in many cases not satisfactory for power integrated circuits since minority carrier conduction through the semiconductor substrate (on which the active part of the device is formed) can take place and interference between adjacent devices is therefore difficult to prevent. In addition, JI bipolar devices (such as the lateral IGBT) also suffer from parasitic mobile carrier plasma stored in the semiconductor substrate in the on-state which has to be removed during turn-off. This decreases dramatically the switching speed of the devices.
In SOI technology, a buried insulating layer is used to isolate vertically the top semiconductor layer from the bottom semiconductor layer and, accordingly, current conduction is principally restricted to the top semiconductor layer and there is practically no current in the bottom semiconductor layer in any mode of operation. Horizontal or lateral isolation in SOI is typically provided via trenches which are filled with oxide or by use of the known LOCOS (xe2x80x9clocal oxidation of siliconxe2x80x9d) isolation. SOI technology offers better isolation than JI technology because the buried insulating layer prevents current conduction and plasma formation in the substrate.
High voltage semiconductor devices have incorporated within the body of the device a high voltage junction that is responsible for blocking the voltage. This junction includes a relatively lowly doped semiconductor layer which withstands the largest portion of the voltage across the main terminals when the device is in the off-state and operating in the voltage blocking mode. This layer is commonly referred to as the drift region or layer and is partially or fully depleted of minority carriers during this operating mode. Ideally, the potential is equally distributed along the drift region between the two ends of the drift region. However, as shown by the 1-D Poisson equation, for a given doping of the drift region, the distribution of the electric field has a triangular shape or, when fully depleted, a trapezoidal shape. Since the area underneath the electric field can be approximated as the breakdown voltage when the peak of the electric field reaches the critical electric field in the semiconductor, it is obvious that for a 1-D junction, the lower the doping of the drift layer, the higher the breakdown voltage. However, for majority carrier devices such as MOSFET types, known as LDMOSFETs, the on-state resistance of the drift layer is inversely proportional to the doping of the drift layer. Since a low on-resistance is desired for a high voltage switch, it follows that a low doping concentration affects the on-state performance of the device. In addition for lateral devices, the critical electric field at the surface is smaller than in the bulk, adding further difficulties in designing high voltage lateral devices.
The introduction of the RESURF (Reduced Surface Field Effect) technique for JI devices allows an increase in the breakdown voltage of lateral devices through the use of an additional vertical junction formed between the drift region and the semiconductor substrate. FIG. 1a shows schematically a conventional JI diode using the RESURF effect. This diode is provided as part of a conventional lateral power device such as a lateral transistor, LDMOSFET or LIGBT. FIG. 1a also shows the distribution of the potential lines and the edge of the depletion region during the voltage blocking mode. It can be noted that the drift layer 1 is fully depleted but the semiconductor substrate 2 is not fully depleted. The potential lines bend as they drop in the substrate, from the vertical direction towards the horizontal direction, such that below the high voltage terminal 3, the potential lines are practically parallel to the bottom surface 4 of the substrate 2. This is because the thickness of the semiconductor substrate 2 is relatively large (typically 300 xcexcm) compared to the vertical extension of the depletion region from the top surface 5 into the substrate 2 (typically 60 xcexcm for a 600V device). Hence, the semiconductor substrate 2 is not fully depleted when the breakdown of the device occurs. It is known that a lateral JI diode can achieve breakdown voltages equivalent to those of vertical diodes, in spite of the reduced surface critical electric field. Nevertheless, as shown in FIG. 1a, even an optimised electric field distribution using the RESURF concept is far from being ideal (i.e. rectangular in shape). In addition as already mentioned, the JI devices suffer from high leakage currents and very poor isolation, which makes integration within a power integrated circuit very difficult.
FIG. 1b shows a conventional SOI diode which is typically found as part of a SOI lateral high voltage power device. The structure can be made using the known wafer bonding, Unibond or SIMOX SOI technologies. Other technologies such as Silicon-on-Diamond (SOD) are also known. FIG. 1b also shows the equi-potential line distribution during the voltage blocking mode. It can be seen that the potential lines crowd towards the edges of the drift layer 1, resulting in a poor RESURF effect. Increasing the thickness of the buried oxide 6 helps to redistribute the potential lines more evenly at the top surface 5. However, in general, the breakdown voltage is still below that of a JI device or JI diode as shown in FIG. 1a. Again, the potential lines in the drift layer 1 and the buried silicon oxide insulating layer 6 below the high voltage terminal are practically aligned to the horizontal surface. This is due to the fact that the semiconductor substrate 2 is not entirely depleted. The result is that all the potential lines have to crowd into the drift layer 1 and insulating layer 6 in the case of SOI and moreover have to align parallel to the insulating layer 6/semiconductor substrate 2 interface. This creates an uneven distribution of the potential lines at the top surface 5 which results in high electric field peaks and therefore lower breakdown voltages. In addition, for SOI devices, the conservation of the perpendicular component of the electric flux density D=∈E at the top of the semiconductor layer 1/buried oxide 6 interface limits the maximum voltage that the buried oxide 6 can sustain before the critical electric field in the semiconductor layer 1 at the interface is reached. This vertical breakdown yields a very strong limitation on the maximum voltage rating achievable for a given buried oxide thickness.
Thus, in summary, in both JI and SOI devices, the potential lines have to bend from a vertical orientation to a horizontal or lateral orientation and the potential distribution in the drift layer is far from ideal.
Moreover, when a power integrated circuit made in thin SOI technology comprises at least a half-bridge configuration, which involves two power devices operating in different modes, the device operating in the high side mode may suffer from pinch-off of the drift region during the on-state. This is due to the high electric field in the drift region caused by the high negative potential created in the semiconductor substrate with respect to the potential of one of the main terminals of the high-side device.
It is therefore apparent that the semiconductor substrate in the SOI technology is not passive in all operation modes and its presence results in a poor distribution of the potential lines during the voltage blocking mode, which may cause premature breakdown commonly at the surface of the semiconductor or at the buried oxide/top semiconductor interface due to vertical breakdown. The JI approach suffers from very poor isolation within the power integrated circuit and the breakdown voltage, although generally higher than in the SOI devices, is still lower than would be preferred.
For discrete devices or hybrid circuits used in high voltage or power electronics, it is preferred that the main terminals have a vertical orientation and are placed at opposite sides of the wafer (e.g. with the low voltage terminal at the top and the high voltage terminal at the bottom). These devices are referred to as vertical high voltage/power devices. Compared to lateral devices, the current flow between the main terminals is principally vertical and this results in a larger current capability and a higher breakdown voltage. Such devices are however difficult to use in integrated circuits. Example of known high voltage/power devices are DMOS and Trench MOSFETs, DMOS and Trench IGBTs and Cool MOS.
For an optimised trade-off between on-state/switching/breakdown performance, the vertical devices require a narrow drift region that is preferably fully depleted at full voltage blocking. Such a layer may have a thickness from 6 xcexcm to 180 xcexcm for devices rated from 50 V to 1.2 kV. Commonly the drift layer lies on a highly doped semiconductor substrate. The semiconductor substrate however introduces a series of negative effects on the general performance of the device. First, it introduces a parasitic resistance, which leads to increased on-state power losses. Secondly, for bipolar devices with anode injection such as IGBTs, since the doping of the substrate is high, to reduce the power losses in the substrate resistance, the injection from the substrate which acts as the anode (emitter) of the device is in most cases too strong, leading to high transient switching losses and slow turn-off due to the a large amount of plasma stored inside the drift region during on-state. Thirdly, the substrate introduces a thermal resistance which prevents effective dissipation of heat to an external sink placed at the bottom of the device. Finally, if vertical devices are to be used in integrated circuits, the presence of the thick semiconductor substrate makes isolation between adjacent devices very difficult.
There have been numerous prior proposals for increasing the breakdown voltage of semiconductor devices, particularly power semiconductor devices. Examples are disclosed in U.S. Pat. Nos. 5,241,210, 5,373,183, 5,378,920, 5,430,316, 5,434,444, 5,463,243, 5,468,982, 5,631,491, 6,040,617, and 6,069,396. However, none of these prior art proposals has tackled the problem of increasing the breakdown voltage by a detailed consideration of the electric potential lines in the drift region.
In WO-A-98/32009, there is disclosed a gas-sensing semiconductor device. A gas-sensitive layer is formed over a MOSFET heater which is used to heat the gas-sensitive layer. The substrate on which the device is formed is back-etched to form a thin membrane in the sensing area. It should be noted that the MOSFET heater is a low voltage device (and as such does not have a drift region) and, furthermore, the thin membrane is formed below the MOSFET heater solely to facilitate heating of the sensing area to very high temperatures and not to affect the field or potential lines in the device.
U.S. Pat. No. 5,895,972 discloses a method and apparatus for cooling a semiconductor device during the testing and debugging phases during development of a device. In place of conventional heat slugs such as copper, a heat slug of material that is transparent to infra red is fixed to the device. A diamond heat slug is disclosed as preferred. It is disclosed that the substrate on which the device is formed can be thinned prior to applying the infra red transparent heat slug to the device. The purpose of this thinning of the substrate is to reduce transmission losses that occur during optical testing and debugging of the device using infra red beams. There is no discussion of the type of semiconductor device to which the heat slug is applied and there is no disclosure that the device is a power device having a drift region. Moreover, as stated, the purpose of the thinning of the substrate and application of the heat slug is solely to facilitate testing of the device using optical testing and debugging. This process is carried out during development of the device. The heat slug is not used during normal operation of the device.
There have been a number of proposals in the prior art for semiconductor devices which make use of a so-called membrane. Examples include U.S. Pat. No. 5,420,458, WO-A-94/22167, U.S. Pat. Nos. 3,689,992 and 6,008,126. In the case of each of these prior art proposals, the semiconductor device is not a power device and thus does not have a drift region. In each case, the membrane arrangement is used to provide for isolation between semiconductor devices in an integrated circuit or between regions within a semiconductor device and/or to remove or lower coupling parasitic capacitances. In each case, since these are low voltage devices, the breakdown voltage is virtually unaffected by the membrane structure.
According to a first aspect of the present invention, there is provided a power semiconductor device having an active region that includes a drift region, at least a portion of the drift region being provided in a membrane having opposed top and bottom surfaces, the top surface of the membrane having electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region, the bottom surface of the membrane not having a semiconductor substrate positioned adjacent thereto.
According to a second aspect of the present invention, there is provided a power semiconductor device having an active region that includes a drift region provided in a layer, the layer being provided on a semiconductor substrate, at least a portion of the semiconductor substrate below at least a portion of the drift region being removed such that said at least a portion of the drift region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed, the top surface of the membrane having electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region.
According to a third aspect of the present invention, there is provided a power semiconductor device having an active region that includes a drift region, at least a portion of the drift region being provided in a membrane having opposed top and bottom surfaces, at least one electrical terminal connected directly or indirectly to the top surface and at least one electrical terminal connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region, the bottom surface of the membrane not having a semiconductor substrate positioned adjacent thereto.
According to a fourth aspect of the present invention, there is provided a power semiconductor device having an active region that includes a drift region provided in a layer, the layer being provided on a semiconductor substrate, at least a portion of the semiconductor substrate below at least a portion of the drift region being removed such that said at least a portion of the drift region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed, and at least one electrical terminal connected directly or indirectly to the top surface and at least one electrical terminal connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region.
The said at least a portion of the drift region is fully or substantially fully depleted of mobile charge carriers when a voltage is applied across terminals of the device. In the first and second aspects of the present invention, the potential lines in said at least a portion of the drift region are substantially perpendicular to the top and bottom surfaces of the membrane and substantially uniformly spread laterally across said at least a portion of the drift region. This is turn leads to a higher breakdown voltage which may approach the ideal or theoretical limit. In the third and fourth aspects, the potential lines in said at least a portion of the drift region are substantially parallel to the top and bottom surfaces of the membrane and substantially uniformly spaced vertically across said at least a portion of the drift region.
Thus, in the preferred embodiments, the absence of the semiconductor substrate under at least a portion of the depletion region in lateral devices leads to enhanced breakdown ability due to a more favourable electric field and potential distribution within the drift region of the power device. For vertical devices, the absence of the semiconductor substrate allows the formation of a thin drift region and removes parasitic effects such as the parasitic series electrical resistance and substrate thermal resistance.
Power devices typically operate with a voltage in the range 30V to 1.2 kV and a current in the range 100 mA to 50 A. Their application may range from domestic appliances, electric cars, motor control, and power supplies to RF and microwave circuits and telecommunication systems.
It will be appreciated that the terms xe2x80x9ctop xe2x80x9d and xe2x80x9cbottomxe2x80x9d, xe2x80x9cabovexe2x80x9d and xe2x80x9cbelowxe2x80x9d, and xe2x80x9clateralxe2x80x9d and xe2x80x9cverticalxe2x80x9d, are all used in this specification by convention and that no particular physical orientation of the device as a whole is implied.
The so-called membrane power device of the present invention may be of many different types, including for example a diode, a transistor, a thyristor, a MOS controllable device such as a MOSFET, an insulated gate bipolar transistor (IGBT), a double gate device, etc.
In the preferred embodiments discussed further below, there is provided a high voltage, power device with high breakdown voltage capacity coupled with excellent isolation and reduced self-heating.
The arrangement may be such that only part of the drift region is provided in the membrane.
In the first and second aspects, where only a part of the drift region is provided in the membrane, preferably the high voltage terminal end of the drift region is contained within the membrane; the remainder of the drift region, including the low voltage terminal end, may remain outside the membrane.
In the third and fourth aspects, the device edge termination may be provided outside the membrane while the active region which includes part of the drift region is provided within the membrane.
In any aspect, the whole of the drift region may be provided in the membrane.
At least one isolation layer may surround the drift region. The at least one isolation layer may be provided in said membrane or in a separate membrane to extend from the top surface of the membrane to the bottom surface of the membrane.
At least one isolation layer may surround the drift region and be provided outside the membrane.
The or at least one isolation layer may be provided by electrically insulating material. The or at least one isolation layer may be provided by a highly doped semiconductor layer which in use is biased to provide a junction that is reverse-biased or biased below the forward-bias level.
There may be provided at least one additional power device having a drift region at least a portion of which is provided on said membrane or on a separate membrane . The separate membrane is preferably formed over the same original substrate and preferably in the same fabrication step with the or each other membrane provided in the device.
There may be provided at least one low voltage device. Said at least one low voltage device may be provided in said membrane. Alternatively, said at least one low voltage device may be provided outside said membrane. In that case, said at least one low voltage device may be provided in a further membrane, said further membrane being preferably formed over the same original substrate and preferably within the same fabrication step with the other membranes provided in the device. In either case, this arrangement provides a power integrated circuit. The low voltage device or devices may be for example a bipolar or CMOS circuit. Such low voltage power devices may form driving, protection or processing circuits. In the preferred embodiments discussed below, the membrane power devices are well isolated both vertically and laterally from such low voltage devices. The vertical isolation is achieved by virtue of the absence of the parasitic substrate beneath the active region of the power device. Lateral isolation can be achieved as briefly described above by one or more isolation layers provided preferably in a membrane from the top to the bottom surface of the membrane or outside the membrane.
There may be at least one isolation layer providing electrical isolation between adjacent devices. The said isolation layer may be placed on a further membrane, said further membrane preferably being formed over the same original substrate and preferably within the same fabrication step with the or each other membrane provided in the device.
In the first and second aspect of the present invention, the device may comprise an electrically insulating and thermally conductive layer adjacent to the bottom surface of the membrane. The electrically insulating and thermally conductive layer is used to help remove a large part of the heat that might otherwise be trapped within the membrane when the power device is operating. The layer may be of any suitable material such as for example polycrystalline diamond, amorphous diamond, boron nitride, aluminium oxide, etc. The material is preferably formed by blanket deposition as a layer by sputtering or chemical vapor deposition or any other suitable technique. The layer may entirely fill the space under the membrane or may be provided as a thin layer under the membrane and which follows the side walls and the bottom surface of any remaining substrate. The layer is preferably in thermal contact with a heat sink.
In the third and fourth aspects, the bottom terminal may be electrically and thermally conductive. The bottom terminal may be made of a metal or a combination of metals such as aluminium, copper etc. The bottom terminal may fill the space under the membrane. In a preferred embodiment, the bottom terminal is provided as a thin layer under the membrane that follows down side walls of any remaining substrate and under the main bottom surface of the device. This layer is preferably in thermal contact with an external heat sink. Alternatively, more than one bottom terminal, in the form of thin layers isolated from one another, can be placed at the bottom of one or separate membranes.
The membrane may comprise a semiconductor layer provided on an electrically insulating layer. The electrically insulating layer may be an oxide layer as formed in for example known SOI technology. Where substrate is etched away to form the membrane, such an oxide layer conveniently acts as an etch stop, which assists in the formation of the membrane. In the third and fourth aspects, this layer is removed to provide access for the terminal layer to be provided at the bottom.
In the first and second aspects, the device may comprise a mechanically strong and electrically insulating layer provided under the membrane. The mechanically strong and electrically insulating layer provides structural support to the membrane and also acts to minimise the risk of membrane rupture.
In any aspect, the drift region may have a non-uniform doping profile. This helps to ensure that the potential lines in the drift region are substantially uniformly spread across the drift region. This is turn leads to a higher breakdown voltage which may approach the ideal or theoretical limit. The doping concentration of the drift region at a high voltage terminal side of the device is preferably relatively high and the doping concentration of the drift region at a low voltage terminal side of the device is preferably relatively low. The doping concentration of the drift region may vary linearly from one side of the drift region to the other. This serves to improve further the breakdown capability of the device.
In the first and second aspects, the drift region may comprise at least two semiconductor layers of alternating conductivity type arranged one above the other and in contact with each other. In use, these two or more semiconductor layers of alternating conductivity type provide a semiconductor junction in a vertical direction such that the drift region can be fully depleted of mobile charge carriers when a voltage is applied across terminals of the device. This again helps to ensure that the potential lines in said at least a portion of the drift region are substantially perpendicular to the top and bottom surfaces of the membrane and substantially uniformly spread laterally across said at least a portion of the drift region. This is turn leads to a higher breakdown voltage which may approach the ideal or theoretical limit.
In any aspect, the drift region may comprise a plurality of laterally adjacent semiconductor regions of alternating conductivity type. These laterally adjacent semiconductor regions of alternating conductivity type form plural transverse junctions in the xe2x80x9czxe2x80x9d direction of the device, which again helps to ensure that the potential lines in said at least a portion of the drift region are substantially uniformly spread across said at least a portion of the drift region. This is turn leads to a higher breakdown voltage which may approach the ideal or theoretical limit.
In any aspect, the drift region may comprise a plurality of laterally adjacent semiconductor cells of alternating conductivity type arrayed around the plane of the device. The cells may be arranged in a regular or an irregular pattern. Either arrangement again helps to ensure that the potential lines in said at least a portion of the drift region are substantially uniformly spread across said at least a portion of the drift region. This in turn leads to a higher breakdown voltage which may approach the ideal or theoretical limit.
The device may comprise a termination region adjacent to and in contact with the drift region, said termination region being provided to reduce the effect of premature breakdown at the edge of the drift region. At least a portion of the said termination region may be placed inside the membrane. At least a portion of the said termination region may be placed outside the membrane and above any semiconductor substrate. The drift region may be more highly doped than at least a portion of the termination region. The drift region may be more highly doped than the semiconductor substrate.
According to a fifth aspect of the present invention, there is provided a method of forming a power semiconductor device having an active region that includes a drift region, the method comprising the steps of: forming, in a layer provided on a semiconductor substrate, a power semiconductor device having an active region that includes a drift region; and, removing at least a portion of the semiconductor substrate below at least a portion of the drift region such that said at least a portion of the drift region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed.
It is preferred that the substrate be removed as the last or one of the last steps in the device fabrication process. In that way, the substrate provides support for the device for as long as possible during the fabrication process.
Said at least a portion of the semiconductor substrate may be removed by wet etching.
Said at least a portion of the semiconductor substrate may be removed by dry etching.
Said at least a portion of the semiconductor substrate may be removed using a buried insulating layer as an etch stop. The burial layer may be part of a Silicon-on-Insulator (SOI) structure.
At least one semiconductor layer may be introduced by implantation, diffusion or deposition from the back-side of the device following the formation of the membrane.
A bottom terminal layer may be applied to the bottom of the membrane, said bottom terminal layer being in contact with at least one semiconductor layer within the membrane.
The method may comprise applying an electrically insulating and thermally conductive layer adjacent the bottom surface of the membrane. The electrically insulating and thermally conductive layer may be applied by a (preferably blanket) deposition process.
Alternatively the method may comprise applying an electrically and thermally conductive layer which acts as an electrode (terminal) adjacent the bottom surface of the membrane. The layer may be applied by a blanket deposition.
In formation of the devices and in the methods described above, one or more of bipolar, CMOS, Bi-CMOS, DMOS, SOI, trench technology or known integrated circuit fabrication steps may be employed.
In the devices and methods described above, the drift region may comprise at least one of silicon, silicon carbide, diamond, gallium nitride and gallium arsenide.
Where provided, at least one of the insulating layers may comprise one of silicon dioxide, nitride, diamond, aluminium oxide, aluminium nitride and boron nitride.